A diode having a trench provided on an upper surface of a silicon substrate is known. For example, in a semiconductor device having a diode and an IGBT on a single silicon substrate (a so-called RC-IGBT (Reverse conducting insulated gate bipolar transistor)), a trench-type gate electrode is provided in an IGBT field, and an electrode arranged in a trench is provided also in a diode field, similar to the gate electrode. In the diode having such a trench electrode, an interlayer insulating film is arranged to cover an upper surface of the silicon substrate, and an upper electrode layer (anode electrode) is arranged on the interlayer insulating film. The trench electrode is insulated from the upper electrode layer by the interlayer insulating film. Further, a contact hole is provided in the interlayer insulating film, and the upper electrode layer is provided also within the contact hole. The upper electrode layer is connected to the silicon substrate in the contact hole. In the diode having this structure, the contact hole is recessed in a concave shape relative to the upper surface of the interlayer insulating film, and the upper electrode layer is formed along the concave-shaped contact hole. Accordingly, a recess is formed on an upper surface of the upper electrode layer as well. With the recess provided on the upper surface of the upper electrode layer, high thermal stress is more likely to be generated in a vicinity of the recess due to a temperature change upon an operation of the diode. A crack may be generated in the upper electrode layer due to the thermal stress being applied thereto repeatedly.
Japanese Patent Application Publication No. 2014-192351 discloses a semiconductor device that has a substantially flat upper surface of an upper electrode layer. In this semiconductor device, a contact hole with a narrow width is provided in an interlayer insulating film. A thin first metal layer (barrier metal configured of Ti, TiN, etc.) is provided at a bottom of the contact hole. A second metal layer (tungsten) is provided above the first metal layer. The contact hole is filled without any gap by the second metal layer. Since an upper surface of the interlayer insulating film and an upper surface of the second metal layer are arranged at substantially the same height, the aforementioned substantially flat upper surface is configured by these upper surfaces. The upper electrode layer covers the upper surface of the interlayer insulating film and the upper surface of the contact metal layer (that is, the flat surface). Since the upper electrode layer is provided on the flat surface, the upper surface of the upper electrode layer is also flattened. Due to this, the thermal stress is less likely to be generated in the upper electrode layer, and the crack is less likely to be generated. The upper electrode layer is connected to the silicon substrate via these first metal layer and second metal layer. By adapting this technique to the aforementioned diode (diode having trench electrode), the upper electrode layer of the diode can be flattened.
Japanese Patent Application Publication No. 2013-048230 discloses a diode including a barrier region and a pillar region. More specifically, in this diode, an anode region, a barrier region, a pillar region, a drift region, and a cathode region are provided in a silicon substrate. The anode region is a p-type region connected with a low resistance to an upper electrode layer (anode electrode). The barrier region is an n-type region provided under the anode region. The pillar region is an n-type region extending from a position in contact with the upper electrode layer to a position in contact with the barrier region. A high barrier (a so-called Schottky barrier) against current flowing from the pillar region toward the upper electrode layer is present between the pillar region and the upper electrode layer. The drift region is an n-type region provided under the barrier region. An n-type impurity concentration of the drift region is lower than an n-type impurity concentration of the barrier region. The cathode region is provided under the drift region, and is an n-type region connected to a lower electrode layer (cathode electrode). An n-type impurity concentration of the cathode region is higher than the n-type impurity concentration of the drift region.
In the diode of Japanese Patent Application Publication No. 2013-048230, when a potential of the upper electrode layer is increased, electrons start to flow from the lower electrode layer toward the upper electrode layer through the cathode region, the drift region, the barrier region, and the pillar region. That is, the electrons flow in the diode at a point when the potential of the upper electrode layer hasn't fully increased. Since the barrier region is connected to the upper electrode layer via the pillar region, a potential difference between the barrier region and the upper electrode layer is small at this point. Due to this, a potential difference is less likely to occur at a pn junction at an interface between the barrier region and the anode region, and the pn junction does not turn on at this point. When the potential of the upper electrode layer is further increased, the current by the aforementioned electrons increases, and the potential difference between the barrier region and the upper electrode layer becomes larger. When this potential difference reaches a predetermined potential difference, the pn junction at the interface between the barrier region and the anode region turns on, and holes flow into the drift region from the upper electrode layer through the anode region and the barrier region. As above, in this diode, the electrons flow through the barrier region and the pillar region before when the pn junction at the interface between the barrier region and the anode region turns on. Due to this, a timing at which the pn junction turns on is delayed, and the holes are suppressed from flowing into the drift region. Thus, upon a reverse recovery operation of this diode, an amount of holes discharged from the drift region to the upper electrode layer is small. Due to this, in this diode, reverse recovery current is small, and a loss generated upon the reverse recovery operation is suppressed. Further, in a state where a reverse voltage is applied to the diode, due to the presence of the high Schottky barrier between the pillar region and the upper electrode layer, leak current flowing through the pillar region is suppressed.